The present invention relates to the manufacturing of semiconductor devices, and more particularly, to copper and copper alloy metallization in semiconductor devices.
The escalating requirements for high density and performance associated with ultra large scale integration (ULSI) semiconductor device wiring are difficult to satisfy in terms of providing sub-micron-sized, low resistance-capacitance (RC) metallization patterns. This is particularly applicable when the sub-micron-features, such as vias, contact areas, lines, trenches, and other shaped openings or recesses have high aspect ratios (depth-to-width) due to miniaturization.
Conventional semiconductor devices typically comprise a semiconductor substrate, usually of doped monocrystalline silicon (Si), and a plurality of sequentially formed inter-metal dielectric layers and electrically conductive patterns. An integrated circuit is formed therefrom containing a plurality of patterns of conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns of vertically spaced metallization levels are electrically interconnected by vertically oriented conductive plugs filling via holes formed in the inter-metal dielectric layer separating the metallization levels, while other conductive plugs filling contact holes establish electrical contact with active device regions, such as a source/drain region of a transistor, formed in or on a semiconductor substrate. Conductive lines formed in trench-like openings typically extend substantially parallel to the semiconductor substrate. Semiconductor devices of such type according to current technology may comprise five or more levels of metallization to satisfy device geometry and microminiaturization requirements.
A commonly employed method for forming conductive plugs for electrically interconnecting vertically spaced metallization levels is known as xe2x80x9cdamascenexe2x80x9d type processing. Generally, this process involves forming a via opening in the inter-metal dielectric layer or interlayer dielectric (ILD) between vertically spaced metallization levels. The via hole is subsequently filled with metal to form a via electrically connecting the vertically spaced apart metal features. The via opening is typically formed using conventional photolithographic and etching techniques. After the via opening is formed, the via is filled with a conductive material, such as tungsten (W), using conventional techniques, and the excess conductive material on the surface of the inter-metal dielectric layer is then typically removed by chemical mechanical planarization (CMP).
A variant of the above-described process, termed xe2x80x9cdual damascenexe2x80x9d processing, involves the formation of an opening having a lower contact or via opening section which communicates with an upper trench section. The opening is then filled with a conductive material to simultaneously form a contact or via in contact with a conductive line. Excess conductive material on the surface of the inter-metal dielectric layer is then removed by CMP. An advantage of the dual damascene process is that the contact or via and the upper line are formed simultaneously.
High performance microprocessor applications require rapid speed of semiconductor circuitry, and the integrated circuit speed varies inversely with the resistance and capacitance of the interconnection pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. If the interconnection node is routed over a considerable distance, e.g., hundreds of microns or more, as in sub-micron technologies, the interconnection capacitance limits the circuit node capacitance loading and, hence, the circuit speed. As integration density increases and feature size decreases, in accordance with sub-micron design rules, the rejection rate due to integrated circuit speed delays significantly reduces manufacturing throughput and increases manufacturing costs.
One way to increase the circuit speed is to reduce the resistance of a conductive pattern. Conventional metallization patterns are typically formed by depositing a layer of conductive material, notably aluminum (Al) or an alloy thereof, and etching, or by damascene techniques. Al is conventionally employed because it is relatively inexpensive, exhibits low resistivity and is relatively easy to etch. However, as the size of openings for vias/contacts and trenches is scaled down to the sub-micron range, step coverage problems result from the use of Al. Poor step coverage causes high current density and enhanced electromigration. Moreover, low dielectric constant polyamide materials, when employed as inter-metal dielectric layers, create moisture/bias reliability problems when in contact with Al, and these problems have decreased the reliability of interconnections formed between various metallization levels.
One approach to improved interconnection paths in vias involves the use of completely filled plugs of a metal, such as W. Accordingly, many current semiconductor devices utilizing VLSI (very large scale integration) technology employ Al for the metallization level and W plugs for interconnections between the different metallization levels. The use of W, however, is attendant with several disadvantages. For example, most W processes are complex and expensive. Furthermore, W has a high resistivity, which decreases circuit speed. Moreover, Joule heating may enhance electromigration of adjacent Al wiring. A further problem is that W plugs are susceptible to void formation, and the interface with the metallization level usually results in high contact resistance.
Another attempted solution for the Al plug interconnect problem involves depositing Al using chemical vapor deposition (CVD) or physical vapor deposition (PVD) at elevated temperatures. The use of CVD for depositing Al is expensive, and hot PVD Al deposition requires very high process temperatures incompatible with manufacturing integrated circuitry.
Copper (Cu) and Cu-based alloys are particularly attractive for use in VLSI and ULSI semiconductor devices, which require multi-level metallization. Cu and Cu-based alloy metallization systems have very low resistivities, which are significantly lower than W and even lower than those of previously preferred systems utilizing Al and its alloys. Additionally, Cu has a higher resistance to electromigration. Furthermore, Cu and its alloys enjoy a considerable cost advantage over a number of other conductive materials, notably silver (Ag) and gold (Au). Also, in contrast to Al and refractory-type metals (e.g., titanium (Ti), tantalum (Ta) and W), Cu and its alloys can be readily deposited at low temperatures formed by well-known xe2x80x9cwetxe2x80x9d plating techniques, such as electroless and electroplating techniques, at deposition rates fully compatible with the requirements of manufacturing throughput.
Another technique to increase the circuit speed is to reduce the capacitance of the inter-metal dielectric layers. Dielectric materials such as silicon oxide (SiO2) have been commonly used to electrically separate and isolate or insulate conductive elements of the integrated circuit from one another. However, as the spacing between these conductive elements in the integrated circuit structure has become smaller, the capacitance between such conductive elements because of the dielectric being formed from silicon oxide is more of a concern. This capacitance negatively affects the overall performance of the integrated circuit because of increased power consumption, reduced speed of the circuitry, and cross-coupling between adjacent conductive elements.
A response to the problem of capacitance between adjacent conductive elements caused by use of silicon oxide dielectrics has led to the use of other dielectric materials, commonly known as low-k dielectrics. Whereas silicon oxide has a dielectric constant of approximately 4.0, many low-k dielectrics have dielectric constants less than 3.5. Examples of low-k dielectric materials include organic or polymeric materials. Another example is porous, low density materials in which a significant fraction of the bulk volume contains air, which has a dielectric constant of approximately 1. The properties of these porous materials are proportional to their porosity. For example, at a porosity of about 80%, the dielectric constant of a porous silica film, i.e. porous SiO2, is approximately 1.5. Still another example of a low-k dielectric material is carbon doped silicon oxide wherein at least a portion of the oxygen atoms bonded to the silicon atoms are replaced by one or more organic groups such as, for example, an alkyl group such as a methyl (CH3xe2x80x94) group.
FIG. 1 shows a cross-section of a metal interconnect portion formed in accordance with prior art methods of processing. A bottom etch stop layer 11 is formed on a substrate 10. The bottom etch stop layer 11 may be made of a number of different materials, such as silicon nitride or silicon carbide. The thickness of the bottom etch stop layer 11 is typically greater than 500 Angstroms in order to provide sufficient etch stop capability. Besides being a diffusion barrier for substrate 10, the bottom etch stop layer 11 serves to protect the substrate 10 from damage during the etching process.
A first dielectric layer 12, which may comprise low k dielectric material, is formed over the bottom etch stop layer 11. A middle etch stop layer 14, which may also comprise silicon nitride or silicon carbide, for example, is formed on the first dielectric layer 12. The thickness of this layer 14 is also greater than 500 Angstroms in order to provide sufficient material to protect the underlying first dielectric layer 12. The pattern of a via is formed in the middle etch stop layer 14. A second dielectric layer 16 is then formed on top of the patterned middle etch stop layer 14. Using conventional photolithography and etching techniques, a second feature is etched in the second dielectric layer 16. This second feature may be a trench, for instance. The etching continues through the pattern opening in the middle etch stop layer 14 and through the first dielectric layer 12, stopping on the bottom etch stop layer 11. Following the etching of the first and second dielectric layers 12, 16, the bottom etch stop layer 11 is etched within the via opening, thereby exposing the substrate 10. Conductive material is then filled within the openings created in the first and second dielectric layers 12, 16 to form a conductive line 18 connected to a conductive via 20. The conductive material may be copper or a copper alloy, for example. When copper is used, typically a barrier metal and a seed layer are deposited prior to the deposition of the copper.
One of the problems associated with the above-described processes and structure in the prior art is the limited choices of material for the middle etch stop layer, layer 14 in FIG. 1. The material needs to be etch resistant. A very commonly used material as an etch stop is silicon nitride, which has a dielectric constant of about 7.5. However, the use of the thick etch stop layer of silicon nitride, needed to assure that the etching will stop on the middle etch stop layer, in conjunction with the low k dielectric layer, partially negates the benefits obtained by the use of low k dielectric material. This is due to the increased combined capacitance of the etch stop layer and the dielectric layer. The same reasoning holds true for the bottom etch stop layer 11 in prior art FIG. 1.
Focus in the industry has therefore recently been turned to avoiding stop layers or employing stop layers with lower k values than silicon nitride. For example, silicon carbide, with a k value of about 4 to 5, is one of the most frequently considered films. However, films with lower k values typically do not function as well in the role of an etch stop as they etch too fast. The films are therefore made thicker to compensate for the lower etch resistance of the film material. But making the film thicker increases the overall capacitance, which is roughly proportional to the k value multiplied by the thickness of the layer. Hence, increasing the thickness to provide adequate etch stop protection in order to employ a lower k value film at least partially negates the benefits sought in selecting a lower k film to be the etch stop.
There is a need for an improved method of forming a metal interconnect structure that exhibits an improved combined dielectric constant for the dielectric layers and etch stop layers.
This and other needs are met by embodiments of the present invention which provide an interconnect arrangement comprising a first layer, and an etch stop layer on the first layer. This etch stop layer has a thickness that is less than approximately 500 Angstroms. A dielectric layer is provided on the etch stop layer.
By providing an etch stop layer that is less than 500 Angstroms, higher k materials may be employed that are more etch resistant than moderate k materials currently used in damascene processing. Since these higher k materials are more etch resistant, a thinner layer than conventionally used may be employed in the etch stop layers. At the same time, however, the overall dielectric constant of the combined low k dielectric layer and etch stop layer may be improved, despite the use of etch stop material that is higher in dielectric constant value, when only a thin etch stop layer is employed.
The earlier stated needs are also met by other aspects of the present invention which include a method of forming a metal interconnect arrangement comprising the steps of forming an etch stop layer on a first layer to a thickness of less than 500 Angstroms, and forming a top dielectric layer on the etch stop layer.
The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.